Microelectronic dies are typically manufactured on semiconductor wafers or other types of workpieces using sophisticated equipment and processes. The individual dies generally include a plurality of bond-pads coupled to integrated circuits. The bond-pads provide external contacts through which data signals, supply voltage, and other electrical signals are transmitted to and from the integrated circuits. Demand for these components requires ever higher performance and smaller packaging. To meet this demand, it has become common practice to stack dies to achieve more memory or computing power in the same unit of space or footprint. This technique reduces the footprint of the devices but increases the height of the package. The same demand for small, powerful devices limits the effectiveness of this technique beyond a certain height threshold depending on the device and its use. Another adverse effect of taller die packages is the increased latency caused by the necessarily longer wirebonds between the upper die(s) and the lead frame or interposer substrate.
Most current packaged devices have a logic component that adds functionality not found in earlier microelectronic packages. However, adding a logic component to a stack of dies adds another die that further increases the height of the die stack. FIG. 1 depicts a device 100 with an interposer substrate 104, a first die 106a attached to the interposer substrate 104, and a second die 106b stacked on the first die 106a. The dies 106a-b are electrically connected to the substrate 104 by wirebonds 108 that extend between bond pads 112 on the substrate 104 and bond pads 113 on the dies 106a-b. The device 100 also has a logic component 114 on top of the second die 106b that is electrically connected to the substrate 104 by additional wirebonds 116. As more dies and other layers are stacked onto each other the distance increases between the substrate 104 and both the upper die (e.g., die 106b) and the logic component 114. This increases both the length of the wirebonds 108 and 116, which also increases the latency in the electrical signals and the height of the die stack. Both the height of the device 100 and the length of the wirebonds 108 and 116 affect the performance and viability of devices.
FIG. 2 illustrates another existing device 200 with a substrate 202 and multiple dies 204 stacked on the substrate 202. The dies 204 have through silicon vias (“TSVs”) 206 that interconnect the dies 204 to each other and to the substrate 202, and a logic component 208 is attached to the bottom of the substrate 202 and electrically coupled to the dies 204 and substrate 202 by interlayer wiring 210. The TSVs mitigate latency problems in large die stacks, but TSVs are more expensive than wirebonds. In light of the existing devices 100 and 200, there is a need for cost-effective structural arrangements that can reduce both the latency and overall size of microelectronic device packages.